Warning Limits Register
| EWL | Programmable Error Warning Limit = (EWL + 1) x 8. Possible Limit values: 8, 16, …128. The value of this bit field controls the CANFD_RTIF[EIF] bit. The EWL bit field needs to be transferred using Clock Domain Crossing (CDC) from host to CAN clock domain. During transfer, this bit field is write-locked for the host for a few clocks until CDC is complete. |
| AFWL | Almost Full Warning Limit. The AFWL bit field defines the internal warning limit AFWL_i with nRB being the number of available RB slots. AFWL_i is compared to the number of filled RB slots and triggers the CANFD_RTIF[RAFIF] bit if equal. The valid range of AFWL_i is [1KB nRB]. AFWL = 0 is meaningless and automatically treated as 0x1. Note that AFWL is meant in this rule and not AFWL_i. AFWL_i > nRB is meaningless and automatically treated as nRB. AFWL_i = nRB is a valid value, but note that the CANFD_RTIF[RFIF] bit also exists. |